1. Field of the Invention
This invention relates generally to emitter coupled logic (ECL) and more particularly to ECL latch and flip-flop circuits which operate at reduced voltages.
2. Description of the Related Art
Conventional edge-triggered D-type flip-flops are used in frequency dividers. Such flip-flops are constructed with two edge-triggered latch circuits.
FIG. 1 is diagram showing a graphic symbol for an edge-triggered ECL D-type latch circuit. The edge-triggered latch circuit receives input data signals D and D and transmits output data signals which correspond to the input data signals.
In FIG. 2, a conventional ECL edge-triggered D-type latch circuit is shown. In the following description, the term "bias voltage level" denotes the central voltage level of the logic voltage swing range of a logic signal such as a data signal or clock signal. Referring to FIG. 2, the D-type latch circuit 100 includes four input terminals IN11, IN12, IN13 and IN14, and two output terminals OUT11 and OUT12. A pair of complimentary input data signal D and D having a bias voltage level V.sub.BB11 are applied to input terminals IN11 and IN12, respectively. One clock signal CK having a bias voltage level which is V.sub.BB12 lower than the level V.sub.BB11 is applied to input terminal IN13. Another other clock signal CK, which is a complimentary signal to CK is applied to input terminal IN14.
An output data signal Q corresponding to the input data signal D is transmitted from output terminal OUT11, and the other output data signal Q being a complementary signal of the signal Q is transmitted from output terminal OUT12.
The latch circuit 100 further comprises input circuit 110, data latch 120, clock driver 130 and current source IE11. Input circuit 110 has two resistors R11 and R12 and two NPN bipolar transistors Q11 and Q12. The circuit 110 receives complementary input data signals D and D and generates complementary output data signals Q and Q. The output data signals Q and Q are provided to output terminals OUT11 and OUT12 respectively. Data latch 120 also is made up of two transistors Q13 and Q14. The latch 120 latches the output data signals Q and Q while the clock signal CK is at a high level (and thus the clock signal CK is at a high level).
Clock driver 130 has two transistors Q15 and Q16 whose bases are connected to input terminals IN13 and IN14 respectively. The driver 130 enables data latch 120 to be activated while the clock signal CK is high.
FIGS. 3A and 3B are waveform diagrams which show the voltage levels of the input/output data signals and clock signals which are applied to the ECL D-type latch circuit shown in FIG. 2. Referring to FIGS. 3A and 3B, the bias voltage level V.sub.BB11 of the respective data signals D, D, Q and Q is higher than the bias voltage level V.sub.BB12 of clock signals CK and CK by an amount equal to the base-emitter voltage of a bipolar transistor (i.e., 0.8 volts).
In a cascade of ECL latch circuits, a front (master) latch circuit generally includes output buffers for the next (slave) latch circuit. The output buffers used in a Master-Slave D-type flip-flop circuit employing the latch circuit of FIG. 2 are shown in FIG. 4. The output buffers are made up of two signal generating circuits 141 and 142. Circuit 141 receives an output data signal Q from a front latch circuit (i.e., master latch circuit) and generates data D for the next latch circuit (i.e., slave latch circuit).
As shown in FIG. 4, signal generating circuit 141 includes a transistor Q17, a resistor R13 and a current source The input data signal D is obtained between emitter of the transistor Q17 and current source IE12. Signal generating circuit 142 receives a clock signal CK from an external signal source and generates a clock signal CK for the next latch (i.e., slave latch circuit). The circuit 142 includes a transistor Q18, a resistor R14 and a current source IE13. The data signal CK is obtained between the resistor R14 and the current source IE13.
FIG. 5 is a schematic circuit diagram which illustrates the supply voltage limit in a conventional Master-Slave D-type flip-flop circuit employing the latch circuit and the signal generator shown respectively in FIGS. 2 and 4. It is assumed that base-emitter voltage V.sub.BE of NPN transistor is 0.8 volts and collector-emitter voltage V.sub.CE thereof is 0.5 volts in consideration of signal swing. It is also assumed that, in the latch circuit, the drop voltage across the respective output drive resistors R11 and R12 is 0.4 volts and the voltage drop across the current source IE11 is 0.5 volts.
If the prior art ECL D-type latch circuit is implemented with a Master-Slave flip-flop circuit, as shown in FIG.5, there is a significant current path along the resistor R12' in the master circuit 100', the transistor 17' in the signal generator 141', the transistors Q11 and Q15 and the current source IE11 in the slave circuit 100. This path constrains the minimum supply voltage V.sub.MIN of the latch circuit. The voltage drop V.sub.MIN associated with the current path can calculated as follows: EQU V.sub.MIN =0.4V(R12')+0.8V(Q17')+0.8V(Q11)+0.5V(Q15)+0.5V(IE11)=3.0V
Since 3.0 volts may drop across the path, the minimum supply voltage V.sub.MIN required to operate the conventional latch circuit is greater than or equal to 3.0 volts. Therefore, the prior art ECL latch circuit can not be readily incorporated into semiconductor devices using a power supply voltage VCC that is less than 3.0 volts.
Accordingly, a need remains for an ECL latch circuit that can operate at reduced power supply voltages.